1. Field of the Invention
The present technology relates to high density memory devices based on phase change based memory materials.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
In phase change memory, data is stored by causing transitions in an active region of the phase change material between amorphous and crystalline states. The difference between the highest resistance R1 of the low resistance crystalline set state and the lowest resistance R2 of the high resistance amorphous reset state defines a read margin used to distinguish cells in the crystalline set state from those in the amorphous reset state. The data stored in a memory cell can be determined by determining whether the memory cell has a resistance corresponding to the low resistance state or to the high resistance state, for example by measuring whether the resistance of the memory cell is above or below a threshold resistance value within the read margin.
Materials within the GST-225 family include GeSbTe compositions along the Sb2Te3 and GeTe tie line as reported in “Structural, electric and kinetic parameters of ternary alloys of GeSbTe”, E. Morales-Sanchez, Thin Solid Films 471 (2005) 243-247. It has been observed that conventional phase change memory cells fabricated from materials in the GST-225 family undergo undesired transformation from the amorphous reset state to the crystalline set state at elevated temperatures. The undesired transformation of the phase change material within the active region of memory cells within an array at elevated operation temperatures leads to the creation of false data and the loss of desired stored data. Efforts to improve the thermal stability of GST-225 phase change memory cells have resulted in memory cells that operate at slower set and reset speeds at higher reset currents with a decrease in the difference between the low resistance of the crystalline set state and the high resistance of the amorphous reset state.
It is desirable therefore to provide a phase change memory material with a higher crystallization temperature to prevent undesired transformation from the amorphous reset state to the crystallized set state at elevated operation temperatures. It is further desirable that the phase change memory material maintain a large difference between the range of reset state resistance values and the range of set state resistance values. It is also desirable that the phase change memory material has a higher crystallization temperature while still retaining fast set and reset speeds. Finally, it is desirable that the phase change memory material be capable of being transformed from a set crystalline state to a reset crystalline state at a lower reset current than that of conventional GST-225 phase change memory material.